Vertical Type Nanotube Semiconductor Device

ABSTRACT

A vertical type nanotuhe semiconductor device including a nanotube bit line, disposed on a substrate and in parallel with the substrate and composed of a nanotube with a conductive property, and a nanotube pole connected to the bit line vertically to the substrate and provides a channel through which carriers migrate. By manufacturing the semiconductor device using the bit line composed of the nanotube, cutoff of an electrical connection of the bit line is prevented and an integration density of the semiconductor device can be improved.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/325,964, filed on Jan. 5, 2006, which claims priority from KoreanPatent Application No. 10-2005-0025368, filed on Mar. 28, 2005, thedisclosures of both of which are incorporated herein by reference intheir entirety

FIELD OF THE INVENTION

The present invention relates to integrated circuit devices and, moreparticularly, to integrated circuit devices having nanotube conductivelayers therein.

BACKGROUND OF THE INVENTION

Nanotubes with conductive properties are cylindrical members with highlymicroscopic diameters of several to several tens of nanometers andsignificantly large aspect ratios of about 10˜1,000. Carriers aremigrated by ballistic transport within a nanotube having a generallyuniform resistance along its length. Particularly, a carbon nanotube hascarrier mobility of about 70 times or more than that of silicon at aroom temperature.

Because of excellent electrical characteristics, nanotubes can beapplied to semiconductor devices, flat panel displays, batteries,various sensors, etc. Particularly, in a conventional nanotubesemiconductor device, the nanotube is used as a channel through whichcarriers are migrated or is used as a lower electrode of a capacitor.

A bit line applied to a conventional nanotube semiconductor device canbe fabricated to have a diameter of about several to several hundreds ofnanometers. However, if the bit line of several to several hundreds ofnanometers is fabricated in a typical manner that simply decreases awidth of a conductive material, then grain boundary defects within thebit line may cut off electrical connection.

SUMMARY OF THE INVENTION

Embodiments of the invention include integrated circuit devices havingnanotube elements therein. In some of these embodiments, a device isprovided with a substrate and an electrically conductive nanotube bitline on the substrate. This nanotube bit line is electrically coupled toa field effect transistor. In particular, a field effect transistor isprovided, which has a first current carrying terminal (e.g., drainterminal) electrically connected to the nanotube bit line. The fieldeffect transistor may include a nanotube channel region and a gateelectrode surrounding the nanotube channel region. According to aspectsof these embodiments, the nanotube bit line includes at least onematerial selected from a group consisting of C, ZnO, CdO, In₂O₃, MgO,Al₂O₃, AlN, InN, GaN, Si, AlP, InP, GaP, InAs, GaAs, AlAs, InSb, GaSb,ZnSe, ZnS, CdS, CdSe and BiSb. This nanotube bit line may be doped witha dopant selected from a group consisting of Mg, Zn, Cd, Ti, Li, Cu, Al,Ni, Y, Ag, Mn, V, Fe, La, Ta, Nb, Ga, In, S, Se, P, As, Co, Cr, B, N, Sband H. In some cases, the device may be a dynamic random access memory(DRAM) cell that includes a capacitor having a nanotube electrodeelectrically connected to a second current carrying terminal (e.g.,source terminal) of the field effect transistor. The capacitor may alsoinclude a capacitor having a dielectric layer covering the nanotubeelectrode. Barrier layers may also be provided to improve adhesion andelectrical connections within the memory cell. In particular, a firstelectrically conductive barrier layer may be provided that extendsbetween the electrically conductive nanotube bit line and the nanotubechannel region. A second electrically conductive barrier layer may alsobe provided that extends between the nanotube electrode and the secondcurrent carrying terminal of the field effect transistor. Theseelectrically conductive barrier layers may be formed of a materialselected from a group consisting of Ni, Co, Fe, alumina and carbon-basedconductive materials.

According to another embodiment of the invention, a vertical nanotubesemiconductor device is provided. A bit line is disposed on thesubstrate in parallel with the substrate. This bit line is formed as ananotube with a conductive property. Also, a nanotube pole, which isconnected to the bit line in a vertical direction to the substrate,provides a channel through which carriers migrate. Also, a gateinsulating layer encircling the nanotube pole to a uniform thickness isincluded. A gate electrode encircles the gate insulating layer tocontrol formation of the channel and carrier migration.

The bit line may be formed of a material selected from a groupconsisting of C, ZnO, CdO, In₂O₃, MgO, Al₂O₃, AlN, InN, GaN, Si, Alp,InP, GaP, InAs, GaAs, AlAs, InSb, GaSb, ZnSe, ZnS, CdS, CdSe, BiSb, andcombinations of these materials. The bit line is doped with at least onematerial selected from a group consisting of Mg, Zn, Cd, Ti, Li, Cu, Al,Ni, Y, Ag, Mn, V, Fe, La, Ta, Nb, Ga, In, S, Se, P, As, Co, Cr, B, N,Sb, and H. Additionally, a diameter of the bit line may be in a range of1˜100 nm.

In addition, a first barrier layer for improving a bonding strengthbetween the bit line and the nanotube pole may be included. The firstbarrier layer may be formed of at least one material selected from agroup consisting of Ni, Co, Fe, alumina, and a carbon-based conductivematerial.

The nanotube pole is formed of a material selected from a groupconsisting of C, ZnO, CdO, In₂O₃, MgO, Al₂O₃, AlN, InN, GaN, Si, AlP,InP, GaP, InAs, GaAs, AlAs, InSb, GaSb, ZnSe, ZnS, CdS, CdSe, BiSb, andcombinations of these materials. The nanotube pole may be doped with atleast one material selected from a group consisting of Mg, Zn, Cd, Ti,Li, Cu, Al, Ni, Y, Ag, Mn, V Fe, La, Ta, Nb, Ga, In, S, Se, P, As, Co,Cr, B, N, Sb, and H. A height of the nanotube pole may be the same as alength of the channel.

The gate electrode is one of a single layer formed of a materialselected from the group consisting of amorphous polysilicon, dopedpolysilicon, poly-SiGe, and a conductive metal containing one or moremetal layers. Moreover, the gate electrode may be formed as a pluralityof gate electrodes spaced apart from one another by a predeterminedinterval.

Additional embodiments of the invention include methods of manufacturinga vertical type nanotube semiconductor device. A bit line is formed onthe substrate in parallel with the substrate. The bit line may be ananotube with a conductive property. A nanotube pole that is connectedto the bit line in a vertical direction to the substrate is formed toprovide a channel through which carriers migrate. After forming a gateinsulating layer encircling the nanotube pole to a uniform thickness, agate electrode is formed that encircles the gate insulating layercontrols the formation of the channel.

At this time, the bit line may be formed using a method such as plasmaCVD, thermal CVD, low pressure CVD, and MOCVD.

The first barrier layer may be formed to improve the bonding strengthbetween the bit line and the nanotube pole. After forming a secondinsulating layer covering the substrate on which the bit line is formed,a hole for the barrier layer is formed within the second insulatinglayer to expose the bit line. A first barrier material layer isdeposited to fill the hole for the barrier layer. Also, the firstbarrier layer is formed by removing the first barrier material layer soas to expose and planarize an upper surface of the second insulatinglayer.

The forming of the nanotube pole includes forming a third insulatinglayer that covers the substrate on which the bit line is formed, andforming a nanotube hole within the third insulating layer to expose thebit line. Then, a nanotube material layer is formed to fill the secondcontact hole, and the nanotube pole is formed by removing the nanotubematerial layer to expose and planarize an upper surface of the thirdinsulating layer.

The formation of the nanotube pole may include forming a thirdinsulating layer on the second insulating layer on which the firstbarrier layer is formed, and forming a nanotube hole within the thirdinsulating layer to expose the first barrier layer. After forming ananotube material layer to fill the nanotube hole, the nanotube pole isformed by removing the nanotube material layer to expose and planarizean upper surface of the third insulating layer.

The step of forming the gate insulating layer may include removing thethird insulating layer on which the nanotube pole is formed, and forminga gate insulating material layer encircling the nanotube pole by blanketdeposition. After forming a first mask layer on the nanotube pole andthe gate insulating material layer, the gate insulating layer is formedby removing the gate insulating material layer using the first masklayer as an etch mask.

In some embodiments of the invention, the gate electrode may have aplurality of gate electrodes spaced apart from one another by apredetermined interval. The forming of the plurality of gate electrodesincludes forming the nanotube pole on the second insulating layercovering the substrate where the bit line is formed, and forming thefirst gate electrode on a lower portion of the nanotube pole. Afterforming a sixth insulating layer to expose an upper surface of thenanotube while covering the first gate electrode, the second gateelectrode is formed on an exposed portion of the nanotube pole.

According to further aspects of the embodiments, a capacitor lowerelectrode may be formed, which is composed of a nanotube. This electrodeis formed to be vertically and serially connected to the nanotube pole.The forming of a lower electrode may include forming a fourth insulatinglayer on the substrate on which the nanotube pole, the gate insulatinglayer and the gate electrode have been formed. Then, a lower electrodeis formed to the other end of the nanotube pole.

A second barrier layer may be formed for improving a bonding strengthbetween the nanotube pole and the nanotube lower electrode. Theformation of the second barrier layer includes forming a fourthinsulating layer on the substrate where the nanotube bar, the gateinsulating layer and the gate electrode are formed. After forming ananotube pole recessed with respect to the gate insulating layer thatremoves an upper portion of the nanotube pole, a second barrier materiallayer is formed on the fourth insulating layer to a predeterminedthickness while covering an upper surface of the recessed nanotube pole.Then, the second barrier layer is formed by patterning the secondbarrier material layer to firmly contact the lower electrode that isformed on the nanotube pole. In this case, the lower electrode may beformed by growing the lower electrode composed of the nanotube on thesecond barrier layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an exploded perspective view of a vertical type nanotubesemiconductor device according to a first embodiment of the presentinvention;

FIG. 2 is a cross-sectional view of the vertical type nanotubesemiconductor device of FIG. 1;

FIGS. 3 through 10 are cross-sectional views illustrating a method ofmanufacturing a vertical type nanotube semiconductor device according tothe first embodiment of the present invention;

FIG. 11 is an exploded perspective view of a vertical type nanotubesemiconductor device according to a second embodiment of the presentinvention;

FIG. 12 is a cross-sectional view of the vertical type nanotubesemiconductor device of FIG. 11; and

FIG. 13 is a cross-sectional view illustrating a method of fabricating aplurality of gate electrodes in the vertical type nanotube semiconductordevice according to the second embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described more fully with reference tothe accompanying drawings, in which exemplary embodiments of theinvention are shown. The invention may, however, be embodied in manydifferent forms and should not be construed as being limited to theembodiments set forth herein; rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the concept of the invention to those skilled in the art.

A nanotube semiconductor device according to the present invention has avertical type structure. That is, a bit line formed on a substrate andan active region formed with a channel are arranged in the verticaldirection with respect to the substrate. FIG. 1 is a perspective view ofrespective parts of a vertical type nanotube semiconductor deviceaccording to a first embodiment of the present invention. FIG. 2 is across-sectional view showing major portions of FIG. 1. Referring toFIGS. 1 and 2, the vertical type nanotube semiconductor device includesa bit line part 10, a transistor part 30 and a capacitor part 50. Thebit line part 10 includes a bit line 16 consisting of a nanotube with aconductive property disposed on a substrate 12 in parallel with thesubstrate 12. A first insulating layer 14 for electrical insulation maybe disposed between the substrate 12 and the bit line 16. One end of thebit line 16 is connected to a recessed nanotube pole 44 extendingvertically to the substrate 12. The nanotube pole 44 provides a channelthrough which carriers can migrate. Preferably, the height of thenanotube pole 44 is similar to a length of the channel. A first barrierlayer 32 may be interposed between the bit line 16 and the nanotube pole44 to enhance a bonding strength therebetween. A gate insulating layer40 encircles the nanotube pole 44 to a uniform thickness. A gateelectrode 42 encircles the gate insulating layer 40 and controlsformation of the channel. A capacitor lower electrode 52 is verticallyconnected to the other end of the nanotube pole 44 to be in line withthe nanotube pole 44. At this time, a second barrier layer 48 forimproving a bonding strength may be formed between the recessed nanotubepole 44 and the capacitor lower electrode 52.

A dielectric film 54 is composed of a material with a high dielectricconstant (e.g., ONO or Ta₂O₅). The dielectric film 54 covers the lowerelectrode 52 and the exposed surface of the second barrier layer 48. Anupper electrode 56 is formed by depositing a conductive material, suchas a polycrystalline silicon doped with impurities, on the entiresurface of the dielectric film 54. An upper electrode contact 60 formedwithin a fifth insulating layer 58 is also provided. The upper electrodecontact 60 is electrically connected to the upper electrode 56.

FIGS. 3 through 10 are cross-sectional views illustrating a method ofmanufacturing the vertical type nanotube semiconductor device accordingto the first embodiment. Referring to FIG. 3, the first insulating layer14 for electrical insulation of the substrate 12 from the bit line 16 isformed on the substrate 12. The first insulating layer 14 may be asilicon oxide layer formed through thermal oxidation. The substrate 12may be at least one layer selected from a silicon layer, a GaAs layer, aSiO₂ layer and an alumina layer. Other substrates may also be used. Aconductive line (not shown) or a conductive region (not shown) may beseparately formed within the substrate 12.

The bit line 16 may be formed using any one method selected from plasmaCVD, thermal CVD, low pressure CVD, and MOCVD. When using CVD, acatalyst layer (not shown) may be formed in advance to induce a growthof the nanotube on the substrate 12 or the first insulating layer 14,thereby making a density of the nanotube across the substrate 12 or thefirst insulating layer 14 uniform. Here, the catalyst layer denoteseither a catalyst that becomes a base of the growth of the nanotube oran optional material containing the catalyst. On the other hand, thenanotube may be fabricated without forming the catalyst layer, whenusing MOCVD.

The bit line 16, which is shown as a nanotube, may be formed of amaterial selected from a group consisting of C, ZnO, CdO, In₂O₃, MgO,Al₂O₃, AlN, InN, GaN, Si, AlP, InP, GaP, InAs, GaAs, AlAs, InSb, GaSb,ZnSe, ZnS, CdS, CdSe, BiSb, and an alloy of two or more of thesematerials. The bit line 16 may be doped with at least one materialselected from a group consisting of Mg, Zn, Cd, Ti, Li, Cu, Al, Ni, Y,Ag, Mn, V, Fe, La, Ta, Nb, Ga, In, S, Se, P, As, Co, Cr, B, N, Sb and H.At this time, the bit line 16 may have a diameter of 1˜100 nm.

Referring to FIG. 4, a first barrier layer 32 for improving bondingstrength is formed between the bit line 16 and the nanotube pole 38 (seeFIG. 6). At this time, the first barrier layer 32 may act as thecatalyst layer as described in FIG. 3. The first barrier layer 32 may becomposed of at least one material selected from a group consisting ofNi, Co, Fe, alumina, and a carbon-based conductive material.

In order to form the first barrier layer 32, a second insulating layer18 (e.g., a silicon oxide layer), is formed to cover the substrate 12having the bit line 16 formed thereon. Then, a hole 20 for a barrierlayer is formed in the second insulating layer 18 to partially exposethe bit line 16. The hole 20 for the barrier layer has an upper portionlarge enough to accept the nanotube pole 38 and a lower portion largeenough to firmly contact the bit line 16. Then, a first barrier materialis deposited so as to fill the hole 20. The first barrier material isremoved to expose and planarize the upper surface of the secondinsulating layer 18, thereby forming the first barrier layer 32.

The first barrier layer 32 may be used as a drain of the semiconductordevice according to the first embodiment. If the first barrier layer 32acts as the drain of the semiconductor device, a thickness of the firstbarrier layer 32 may depend upon electrical characteristics of thedrain. In particular, the first barrier layer 32 may need to be thick toreduce drain resistance. If necessary, the nanotube pole 38 is directlyconnected to the bit line 16 without forming the first barrier layer 32.This is because an extra source/drain structure may not be required dueto the formation of the channel by the gate electrode 42.

Referring to FIG. 5, a third insulating layer 34 is formed on the secondinsulating layer 18 having the first barrier layer 32 already formedthereon. Subsequently, a nanotube hole 36 that exposes an upper surfaceof the first barrier layer 32 is formed within the third insulatinglayer 34. The nanotube hole 36 is a space where the nanotube pole 38 isto be formed. The reason why the nanotube pole 38 is grown within thenanotube hole 36 instead of being grown on the first barrier layer 32without being restricted by the nanotube hole 36 is that the dimensionof the nanotube pole 38 can be precisely controlled.

If the nanotube pole 38 is formed without forming the first barrierlayer 32, the third insulating layer 34, (e.g., a silicon oxide layer ora block copolymer), is formed to cover the substrate 12 or the firstinsulating layer 14 having the bit line 16 formed thereon. Thereafter,the nanotube hole 36, which partially exposes the bit line 16, is formedin the third insulating layer 34. The nanotube hole 36 may be formed invarious ways. For example, the block copolymer is partially removed, orthe silicon oxide layer is patterned, to form the nanotube hole 36.

Referring to FIG. 6, a nanotube material layer is formed so as to fillthe nanotube hole 36. Then, the nanotube material layer is removed toexpose and planarize the upper surface of the third insulating layer 34,thereby forming the nanotube pole 38. Similar to the bit line 16, thenanotube material layer may be formed using any one method selected fromplasma CVD, thermal CVD, low pressure CVD, and MOCVD.

The nanotube pole 38 may be formed of a material selected from a groupconsisting of C, ZnO, CdO, In₂O₃, MgO, Al₂O₃, AlN, InN, GaN, Si, AlP,InP, GaP, InAs, GaAs, AlAs, InSb, GaSb, ZnSe, ZnS, CdS, CdSe, BiSb, andan alloy of two or more of these materials. The nanotube pole 38 may bedoped with at least one material selected from a group consisting of Mg,Zn, Cd, Ti, Li, Cu, Al, Ni, Y, Ag, Mn, V, Fe, La, Ta, Nb, Ga, In, S, Se,P, As, Co, Cr, B, N, Sb, and H.

Referring to FIG. 7, to form the gate insulating layer 40, the thirdinsulating layer 34 is removed. Then, a gate insulating material layerthat encircles the nanotube pole 38 is formed by blanket deposition. Afirst mask layer (not shown) for forming the gate insulating layer 40 toa uniform thickness is formed on the nanotube pole 38 and the gateinsulating material layer. After this, the gate insulating materiallayer is removed using the first mask layer as an etch mask to form thegate insulating layer 40. The gate insulating layer 40 may be either asilicon oxide layer or a stacked layer of silicon oxide/siliconnitride/silicon oxide (i.e., ONO layer).

Thereafter, the gate electrode 42 encircling the gate insulating layer40 and controlling the channel formation is formed using a typicaldepositing method. Preferably, the gate electrode 42 is lower than thegate insulating layer 40. The gate electrode 42 may be formed of eithera single layer selected from a group consisting of amorphouspolysilicon, doped polysilicon, poly-SiGe, and a conductive metal or acomposite layer of these materials. The conductive metal may be amaterial selected from a group consisting of a metal such as W and Mo,and a conductive metal nitride such as TiN, TaN or WN.

Referring to FIG. 8, the second barrier layer 48 is formed to improvethe bonding strength between the nanotube pole 38 and the nanotube lowerelectrode 52. The second barrier layer 48 may act as the catalyst layeras described above with reference to FIG. 3. The second barrier layer 48may be formed of at least one material selected from a group consistingof Ni, Co, Fe, alumina, and a carbon-based conductive material. In orderto form the second barrier layer 48, the fourth insulating layer 46 isformed on the second insulating layer 18 on which the nanotube pole 38,the gate insulating layer 40 and the gate electrode 42 have been formed.Then, the fourth insulating layer 46 is planarized to expose thenanotube pole 38. An upper portion of the nanotube pole 38 is removed toform the nanotube pole 44 recessed with respect to the gate insulatinglayer 40. The height of the recessed nanotube pole 44 may be the same asthe channel length. A second barrier material layer is formed on thefourth insulating layer 46 to a predetermined thickness while coveringthe recessed nanotube pole 44. Thereafter, the second barrier materiallayer is patterned to firmly contact the lower electrode 52 to be formedon the recessed nanotube pole 44, thereby forming the second barrierlayer 48.

Referring to FIG. 9, the lower electrode 52 composed of a nanotube isgrown on the second barrier layer 48. Similar to the formation of thebit line 16, the lower electrode 52 may be formed using any one methodselected from plasma CVD, thermal CVD, low pressure CVD, and MOCVD. Thelower electrode 52 may be formed of a material selected from a groupconsisting of C, ZnO, CdO, In₂O₃, MgO, Al₂O₃, AlN, InN, GaN, Si, AlP,InP, GaP, InAs, GaAs, AlAs, InSb, GaSb, ZnSe, ZnS, CdS, CdSe, BiSb, andan alloy of these. The lower electrode 52 may be doped with at least onematerial selected from a group consisting of Mg, Zn, Cd, Ti, Li, Cu, Al,Ni, Y, Ag, Mn, V, Fe, La, Ta, Nb, Ga, In, S, Se, P, As, Co, Cr, B, N,Sb, and H.

Referring to FIG. 10, the dielectric film 54, which is formed of amaterial with a high dielectric constant, (e.g., ONO or Ta₂O₅), thatcovers the lower electrode 52 and the exposed surface of the secondbarrier layer 48, is formed to a uniform thickness. Thereafter, aconductive material such as polycrystalline silicon doped withimpurities is deposited on the entire surface of the dielectric film 54to a uniform thickness, thereby forming the upper electrode 56.Subsequently, as illustrated by FIG. 2, the upper electrode contact 60disposed within the fifth insulating layer 58 that covers the upperelectrode 56 is formed to provide an electrode terminal that may beconnected to another device (not shown).

In the nanotube semiconductor device according to the first embodiment,the nanotube pole or the nanotube pole/nanotube lower electrode isvertically and serially arranged on the bit line, so that an area of thesemiconductor device is minimized. Therefore, an integration density ofthe semiconductor device can be improved.

FIG. 11 is an exploded perspective view of a vertical type nanotubesemiconductor device according to a second embodiment of the presentinvention. FIG. 12 is a cross-sectional view showing major portions ofthe device of FIG. 11. Referring to FIGS. 11 and 12, the vertical typenanotube semiconductor device is largely comprised of the bit line part10, the transistor part 30, and the capacitor part 50. The bit line part10 includes the bit line 16 consisting of the nanotube with theconductive property, and is disposed on the substrate 12 in parallelwith the substrate 12. A first insulating layer 14 may be formed forelectrical insulation between the substrate 12 and the bit line 16. Thenanotube bit line 16 can be formed to have a nanometer dimension, andhardly has a grain boundary in the nanometer dimension, so that anelectrical cutoff does not occur.

One end of the bit line 16 is connected to the recessed nanotube pole 44extending in the vertical direction to the substrate 12. The recessednanotube pole 44 provides the channel through which carriers aremigrated. Preferably, the height of the nanotube pole 44 is the same asthe channel length. The first barrier layer 32 may be interposed betweenthe bit line 16 and the nanotube pole 44 to improve the bondingstrength.

The gate insulating layer 40 encircles the nanotube pole 44 to a uniformthickness. The gate electrode 42 surrounds the gate insulating layer 40,and controls the channel formation. A gate electrode according to thesecond embodiment may be formed of a plurality of gate electrodes 72 and74 spaced apart from each other by a predetermined interval.

The capacitor lower electrode 52 is vertically and serially connected tothe other end of the nanotube pole 44. At this time, the second barrierlayer 48 may be formed to improve the bonding strength between therecessed nanotube pole 44 and the nanotube lower electrode 52.

The dielectric film 54 is composed of a material with a high dielectricconstant (e.g., ONO or Ta₂O₅) that covers the lower electrode 52 and theexposed surface of the second barrier layer 48. The upper electrode 56is disposed on the entire surface of the dielectric film 54 bydepositing a conductive material such as polycrystalline silicon dopedwith impurities. The upper electrode contact 60 is formed within thefifth insulating layer 58 covering the upper electrode 56 electricallyconnects to the outside (see, e.g., FIG. 2).

A method of manufacturing the vertical type nanotube semiconductordevice according to the second embodiment is similar to that for thefirst embodiment described with reference to FIGS. 3 through 9 exceptfor the formation of the gate electrodes, so a description of duplicateparts will be omitted. FIG. 13 is a cross-sectional view illustrating amethod of fabricating the plurality of gate electrodes 72 and 74 in thevertical type nanotube semiconductor device according to the secondembodiment. Referring to FIG. 13, to form the plurality of gateelectrodes 72 and 74, first, the nanotube pole 38 is formed on thesecond insulating layer 18 covering the substrate 12 on which the bitline 16 is formed. Then, the first gate electrode 72 encircles a lowerside surface of the nanotube pole 38 as in the first embodiment. A sixthinsulating layer 76 that exposes an upper portion of the nanotube pole38 but covers the first gate electrode 72 is formed. The second gateelectrode 74 is formed on an exposed side surface of the nanotube pole38.

According to the nanotube semiconductor device of the second embodiment,the nanotube pole or nanotube pole/nanotube lower electrode isvertically and serially formed on the bit line. Thus, an area of thesemiconductor device is minimized. Therefore, an integration density ofthe semiconductor device can be improved.

According to a vertical type nanotube semiconductor device according tothe present invention and a method of manufacturing the same, a bit linecomposed of a nanotube is applied to the vertical type nanotubesemiconductor device. Thus, the cut-off of the electrical connection ofthe bit line in the semiconductor device of nanometer level can beprevented. Furthermore, the bit line is formed on the substrate toembody a semiconductor device with a vertical type transistor, therebyimproving the integration density of the semiconductor device.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention as defined by the following claims.

1.-40. (canceled)
 41. An integrated circuit device, comprising: asubstrate; and a field effect transistor having a nanotube channelregion and a gate electrode surrounding the nanotube channel region, onsaid substrate.
 42. The device of claim 41, wherein the nanotube channelregion comprises a material selected from a group consisting of C, ZnO,CdO, In2O3, MgO, Al₂O₃, AlN, InN, GaN, Si, AlP, InP, GaP, InAs, GaAs,AlAs, InSb, GaSb, ZnSe, ZnS, CdS, CdSe and BiSb.
 43. The device of claim42, wherein the nanotube channel region is doped with a dopant selectedfrom a group consisting of Mg, Zn, Cd, Ti, Li, Cu, Al, Ni, Y, Ag, Mn, V,Fe, La, Ta, Nb, Ga, In, S, Se, P, As, Co, Cr, B, N, Sb and H.
 44. Thedevice of claim 41, wherein said field effect transistor furthercomprises a gate insulating layer extending between the gate electrodeand the nanotube channel region.
 45. The device of claim 44, wherein thegate insulating layer is an oxide/nitride/oxide (ONO) layer.
 46. Thedevice of claim 41, further comprising a capacitor having a nanotubeelectrode electrically connected to a current carrying terminal of saidfield effect transistor.
 47. The device of claim 46, wherein saidcapacitor comprises a capacitor dielectric layer covering the nanotubeelectrode.
 48. The device of claim 41, wherein the nanotube channelregion has a longitudinal axis that extends orthogonal to a surface ofsaid substrate.
 49. The device of claim 41, wherein said field effecttransistor comprises a plurality of spaced-apart gate electrodessurrounding the nanotube channel region.